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Developer Divyansh Agrawal reports that Qwenputer, an experimental build based on Qwen3.5 4B, runs a 32-bit RISC-V CPU within added model weights and uses Gated DeltaNet state as RAM. He says it passes official RISC-V tests and completed an 18-million-instruction free-running test without error; those results are reported by the project author, not independently verified here.
Developer Divyansh Agrawal says he has built Qwenputer, an experimental version of Qwen3.5 4B with a working 32-bit RISC-V CPU compiled into added model weights. The CPU uses the model’s Gated DeltaNet state as addressable RAM and runs through the model’s forward passes, rather than through an external runtime or tool call, according to Agrawal’s report.
Agrawal describes the processor as an RV32IM core, with the Zba extension and a small unit for larger-number arithmetic. It occupies 11 layers added in front of Qwen’s 32 layers. He says the core passes official RISC-V tests, produces results matching QEMU, and ran 18 million instructions continuously without an error. Those benchmarks and implementation details come from the developer’s account; the source provided does not include an independent assessment.
The memory design uses Gated DeltaNet (GDN), a recurrent attention mechanism found in Qwen3.5. Agrawal says he configured the state update so a one-hot address can select a particular row: with the gate set to 1 and write strength beta set to 1, a write replaces the selected value rather than gradually blending with it. A one-hot query can then retrieve that value. The model’s state can serve as fixed-size memory, rather than relying on a key-value cache that grows with the conversation.
The CPU is described as running as Qwen generates a trace of instruction-related tokens, including an address, a value and a step marker. The model can send work to the internal processor using a format resembling a tool call, but Agrawal says no outside tool or execution runtime performs the computation. A small loader, RvChat, places firmware into the GDN state and keeps execution-trace tokens out of Qwen’s layers. The source says the base Qwen weights remain unchanged, with computer weights added on top.
A Processor Runs Within Model Computation
Qwenputer is a demonstration of a different way to combine a language model with computation: instead of asking an external program to execute code, it places a small processor in the model’s own layers and uses recurrent state as working memory. If the reported behavior holds up under outside testing, the project offers a concrete example of model parameters and recurrent state implementing a reproducible instruction set, rather than merely producing text that looks like a calculation.
The distinction matters for both capability and evaluation. An internal CPU could give a model a more reliable route for arithmetic and program execution, while also making it harder to infer how an answer was produced from ordinary text alone. Agrawal’s write-up points to related work on hidden reasoning and internal monitoring, but those are separate follow-up topics, not results established by the CPU demonstration itself. Qwenputer is an experiment, not evidence that a general-purpose processor or computer can replace external hardware.
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How DeltaNet State Becomes RAM
Qwen3.5 uses a hybrid architecture in which, according to Agrawal, three of every four attention layers use Gated DeltaNet. Each head retains a state matrix and updates it as tokens arrive. The ordinary mechanism is designed to manage information over a sequence; Agrawal’s change makes selected rows behave more like exact, addressable storage for the CPU.
The underlying idea of delta-rule memory has prior research. Agrawal cites a 2021 paper by Imanol Schlag, Kazuki Irie and Jürgen Schmidhuber on linear transformers as fast-weight programmers. He characterizes Qwenputer’s contribution as making that memory exact and addressable within a production-model architecture, then compiling a CPU into the layers. He says the compiler sets the added weights directly, without training the model for the task.
The project author says Qwenputer and its code are available through Hugging Face, ModelScope and GitHub. The supplied report does not give a publication date, independent replication, or detailed performance comparisons with conventional CPU execution.
“The CPU runs completely within the forward passes of the model.”
— Divyansh Agrawal, Qwenputer’s developer
Independent Testing Is Still Needed
The source is a project report by the person who built Qwenputer. It does not provide third-party test results, a detailed benchmark methodology, or enough information to compare the CPU’s speed and resource use with external execution. The stated 18-million-instruction run and successful test-suite results should therefore be understood as author-reported claims.
It is also unclear how broadly the model handles programs beyond the examples described, how its reported C and MicroPython execution performs on varied workloads, and what practical limits follow from running instructions as generated tokens. Agrawal describes execution as somewhat slow and says the project is not Linux-class. The available material does not establish whether others have reproduced the results or how the system behaves under independent evaluation.
Code and Replication Will Test the Claims
Agrawal points readers to the project’s model files and GitHub code, which provide a route for technical inspection and replication. The next useful evidence would include independent runs of the RISC-V tests, reproduction of the long free-running instruction test, and published measurements of execution speed and reliability across programs.
No formal review, release schedule, or next benchmark is identified in the supplied report. For now, Qwenputer remains a developer-led experiment; its broader significance will depend on whether other researchers can verify the CPU’s operation and establish what tasks it handles reliably.
Key Questions
What is Qwenputer?
Qwenputer is an experimental Qwen3.5 4B build with a RISC-V CPU compiled into added model weights, according to its developer, Divyansh Agrawal.
Does it use an external code-execution tool?
Agrawal says the CPU runs inside the model’s forward passes and is not invoked through an external runtime or tool. A loader called RvChat sets up firmware and manages the trace, but the report says it does not perform the CPU’s execution externally.
How does the model provide memory to the CPU?
The design uses Gated DeltaNet state as addressable storage. Agrawal says the modified state update lets one-hot addresses write to and read from specific rows.
Has the CPU’s performance been independently verified?
The supplied source reports that the core passes official RISC-V tests and completed an 18-million-instruction run without error. It does not include independent verification, so those results remain claims by the project developer.
Can Qwenputer run ordinary operating systems?
The report says the processor is not Linux-class. It implements RV32IM, with the Zba extension and a small bignum unit, and is described as capable of running C and MicroPython code, though somewhat slowly.
Source: divagr.com
